Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and\r\ndecimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10\r\ndigit recurrence dividers for FPGA architectures.The first one implements a simple restoring shift-and-subtract algorithm, whereas\r\neach of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient\r\ncalculation and carry-save representation of the residuals.More precisely, the quotient digit selection function of the second divider\r\nis implemented fully by means of a ROM, the quotient digit selection function of the third and fourth dividers are based on carrypropagate\r\nadders, and the fifth divider decomposes each digit into three components and requires neither a ROMnor amultiplexer.\r\nFurthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64\r\ndata format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA, and implementation results are given.
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